(1) Field of the Invention
This invention relates to a method of forming conducting metal pillars to provide electrical connection between two levels of electrode patterns.
(2) Description of the Related Art
U.S. Pat. No. 5,248,854 to Kudoh et al. describe a method of forming conducting pillars between two layers of electrode patterns using a method different from the method of this invention. Kudoh et al. describe forming groves in a layer of photoresist and forming electrodes and pillars in the photoresist grooves.
U.S. Pat. No. 5,502,008 to Hayakawa et al. describe a method of forming conducting metal pluge by means of forming holes in a layer of dielectric, depositing a layer of conductor material, and etching back the layer of conducting material to leave conducting material only in the via holes.
U.S. Pat. No. 5,358,902 to Verhaar et al. describes a method of forming conducting metal plugs by means of applying a flowable organic material on a substrate to form an organic layer. Via holes are formed in the organic layer and filled with electrically conductive material. The organic layer is then removed leaving conducting pillars.
U.S. Pat. No. 5,100,838 to Dennison describes a method of forming conducting pillars which includes forming parallel-spaced conductor lines on a substrate, forming insulating spacers on the sidewalls of the conductor lines leaving a gap between the lines, filling the gaps with a conductor film, and etching the film to form conducting pillars.
U.S. Pat. No. 5,118,385 to Kumar et al. describes a method of forming conducting pillars by means of depositing a layer of dielectric over a patterned metal layer, forming via holes in the dielectric, depositing metal into the via holes, and planarizing the top of the structure leaving metal pillars in the via holes.
A paper entitled "0.6 .mu.m Pitch Highly Feliable Multilevel Interconnection Using Hydrogen Silicate Based Inorganic SOG for Sub-Quarter Micron CMOS Technology", by N. Oda et al., 1997 Symposium on VLSI Technology Digest of Technical Papers, pages 79-80 describes an interconnection technology using a low dielectric constant Hydrogen Silicate Based Inorganic Spin On Glass as an insulator.
A paper entitled "Integration of Ultra-Low-k Xerogel Gapfill Dielectric for High Performance Sub 0.18 .mu.m Interconnects", by R. S. List et al., 1997 Symposium on VLSI Technology Digest of Technical Papers, pages 77-78 describes an inter-layer dielectric film having a low dielectric constant.
This invention describes a method of forming conducting metal pillars for interconnecting two levels of electrode patterns. The pillars are etched from a blanket layer of metal deposited on a wafer. The inter-level dielectric is then deposited over the pillars.